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HT82V38 16-Bit CCD/CIS Analog Signal Processor
Features
* Operating voltage: 3.3V (typ.) * Low Power CMOS: 300 mW (typ.) * Power-Down Mode: 10mA (max.) * 16-Bit 30 MSPS A/D converter * Guaranteed wont miss codes * 1~5.85x programmable gain * Correlated double sampling * 250 mV programmable offset * Input clamp circuitry * Internal voltage reference * Multiplexed byte-wide output (8+8 format) * Programmable 3-wire serial interface * 3 .3V digital I/O compatibility * 3-Channel operation up to 30 MSPS * 2-Channel (even-odd) operation up to 30 MSPS * 1-Channel operation up to 20 MSPS * 28-pin SSOP (209mil) package
Applications
* Flatbed document scanners * Film scanners * Digital color copiers * Multifunction peripherals
General Description
The HT82V38 is a complete analog signal processor for CCD imaging applications. It features a 3 channel architecture designed to sample and condition the outputs of trilinear color CCD arrays. Each channel consists of an input clamp, Correlated Double Sampler (CDS), offset DAC and Programmable Gain Amplifier (PGA), multiplexed to a high performance 16-bit A/D converter. The CDS amplifiers may be disabled for use with sensors such as Contact Image Sensors (CIS) and CMOS active pixel sensors, which do not require CDS. The 16-bit digital output is multiplexed into an 8-bit output word that is accessed using two read cycles. The internal registers are programmed through a 3-wire serial interface, and provide adjustment of the gain, offset, and operating mode.
Block Diagram
AVDD AVSS REFT REFB AVDD AVSS DVDD DVSS
V IN R
CDS
+ 9 - B it DAC
PGA BANDGAP R e fe re n c e PGA 3 .1 MUX 1 6 - B it ADC C o n fig u r a tio n R e g is te r MUX R e g is te r 6 RED GREEN BLUE D ig ita l C o n tro l In te rfa c e 16 1 6 :8 MUX 8
OE
V IN G
CDS
+ 9 - B it DAC
DOUT
V IN B
CDS
+ 9 - B it DAC 9
PGA
OFFSET
In p u t C la m p B ia s
G a in R e g is te r s
SC LK SLO AD SDATA
RED GREEN BLUE
O ffs e t R e g is te r s AD CCLK
CDSCLK1
CDSCLK2
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HT82V38
Pin Assignment
CDSCLK1 1 2 3 4 5 6 7 8 9 10 11 12 13 14 CDSCLK2 AD CCLK OE DVDD DVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B ) 28 27 26 25 24 23 22 21 20 19 18 17 16 15 AVDD AVSS V IN R OFFSET V IN G CML V IN B REFT REFB AVSS AVDD SLO AD SC LK SDATA
H T82V38 2 8 S S O P -A
Pin Description
Pin No. 1 2 3 4 5 6 7~14 15 16 17 18, 28 19, 27 20 21 22 23 24 25 26 Note: Pin Name CDSCLK1 CDSCLK2 ADCCLK OE DVDD DVSS D7~D0 SDATA SCLK SLOAD AVDD AVSS REFB REFT VINB CML VING OFFSET VINR I/O DI DI DI DI P P DO DI/DO DI DI P P AO AO AI AO AI AO AI Description CDS Reference Clock Pulse Input CDS Data Clock Pulse Input A/D Sample Clock Input for 3-channels Mode Output Enable, Active Low Internal pull-low 50W Digital Power Digital Ground Digital Data Output Serial Data Input/Output Clock Input for Serial Interface Serial Interface Load Pulse Analog Supply Analog Ground Reference Decoupling Reference Decoupling Analog Input, Blue Internal Reference Output Analog Input, Green Clamp Bias Level Decoupling Analog Input, Red
AI=Analog Input, AO=Analog Output, DI=Digital Input, DO=Digital Output, P=Power
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HT82V38
Absolute Maximum Ratings
Supply Voltage ..........................VSS-0.3V to VSS+4.3V Input Voltage .............................VSS-0.3V to VDD+0.3V Storage Temperature ...........................-50C to 125C Operating Temperature ..............................0C to 70C
Note: These are stress ratings only. Stresses exceeding the range specified under Absolute Maximum Ratings may cause substantial damage to the device. Functional operation of this device at other conditions beyond those listed in the specification is not implied and prolonged exposure to extreme conditions may affect device reliability.
D.C. Characteristics
Symbol Logic Inputs VIH VIL IIH IIL CIN High Level Input Voltage Low Level Input Voltage High Level Input Current Low Level Input Current Input Capacitance 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 0.8VDD 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 5 3/4 0.2VDD 1 1 3/4 V V mA mA pF Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
Logic Outputs VOH VOL High Level Output Voltage Low Level Output Voltage 3/4 3/4 IOH=3mA IOL=3mA DVDD-0.5 3/4 3/4 3/4 3/4 0.5 V V
A.C. Characteristics
Symbol Power Supplies AVDD DVDD AVDD DVDD 3/4 3/4 3/4 3/4 3.15 3.15 3.3 3.3 3.45 3.45 V V Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
Maximum Conversion Rate 3-channel Mode with CDS tMAX 2-channel Mode with CDS 1-channel Mode with CDS Accuracy (Entire Signal Path) ADC Resolution Integral Nonlinear (INL) Differential Nonlinear (DNL) Offset Error Gain Error 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 -1 -100 3/4 16 32 3/4 3/4 5 3/4 3/4 +1 +100 3/4 Bits LSB mV mV %FSR 3/4 3/4 3/4 3/4 3/4 3/4 30 30 20 3/4 3/4 3/4 3/4 3/4 3/4 MPS MPS MPS
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Symbol Analog Inputs RFS Vi Ci Ii Full-scale Input Range Input Limits Input Capacitance Input Current 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 AVSS-0.3 3/4 3/4 1.6/2.0 3/4 10 10 3/4 AVDD+0.3 3/4 3/4 V V pF mA Parameter Test Conditions VDD Conditions Min. Typ. Max. Unit
Amplifiers PGA Gain at Minimum PGA Gain at Maximum PGA Gain Resolution Programmable Offset at Minimum Programmable Offset at Maximum Offset Resolution Clamp DAC Circuit tA Clamp DAC resolution Clamp DAC output voltage at code 0 Clamp DAC output voltage at code F Clamp DAC Step size Clamp DAC deviation (AVDD=3.300V) Temperature Range tA Operating 3/4 3/4 0 3/4 70 C 3/4 3/4 3/4 3/4 3/4 3/4 -50 4 0.45 2.7 0.15 3/4 3/4 3/4 3/4 3/4 50 Bits V V V/Step mV 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 1 5.85 6 -250 250 9 3/4 3/4 3/4 3/4 3/4 3/4 V/V V/V Bits mV mV Bits
Power Consumption Ptot Total Power Consumption 3/4 3/4 3/4 300 3/4 mW
Timing Specification Symbol Clock Parameters tPRA tPRB tPRC tADCLK tC1 tC2 tC1C2 tADC2 tC2ADR tC2ADF tADC1 tAD
AVDD=DRVDD=3.3V, AVSS=DRVSS=0V, Ta=25C, ADCCLK=30MHz unless otherwise stated Parameter Min. Typ. Max. Unit
3-Channel Pixel Rate 2-Channel Pixel Rate 1-Channel Pixel Rate ADCCLK Pulse Width CDSCLK1 Pulse Width CDSCLK2 Pulse Width CDSCLK1 Falling to CDSCLK2 Rising ADCCLK Falling to CDSCLK2 Rising CDSCLK2 Rising to ADCCLK Rising CDSCLK2 Falling to ADCCLK Falling ADCCLK Falling to CDSCLK1 Rising Aperture Delay for CDS Clocks
100 66 50 16 10 10 0 2 2 20 0 3/4
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3
3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4
ns ns ns ns ns ns ns ns ns ns ns ns
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Symbol Serial Interface fSCLK tLS tLH tDS tDH tRDV Data Output tOD Output Delay (output load 10pF) Latency (Pipeline Delay) 3/4 3/4 10 9 3/4 3/4 ns Cycles Maximum SCLK Frequency SLOAD to SCLK Setup Time SCLK to SLOAD Hold Time SDATA to SCLK Rising Setup Time SCLK Rising to SDATA Hold Time SCLK Falling to SDATA Valid 10 10 10 10 10 10 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 3/4 MHz ns ns ns ns ns Parameter Min. Typ. Max. Unit
Functional Description
Integral Nonlinear (INL) Integral nonlinearity error refers to the deviation of each individual code from a line drawn from zero scale through positive full scale. The point used as zero scale occurs 1/2 LSB before the first code transition. Positive full scale is defined as a level 1/2 LSB beyond the last code transition. The deviation is measured from the middle of each particular code to the true straight line. Differential Nonlinear (DNL) An ideal ADC exhibits code transitions that are exactly 1 LSB apart. DNL is the deviation from this ideal value. Thus every code must have a finite width. No missing codes guaranteed to 16-bit resolution indicates that all 4096 codes, respectively, must be present over all operating ranges. Offset Error The first ADC code transition should occur at a level 1/2 LSB above the nominal zero scale voltage. The offset error is the deviation of the actual first code transition level from the ideal level. Gain Error The last code transition should occur for an analog va l u e 1 /2 L S B b e l o w t h e f u l l - sca l e vo l t a g e (2(REFT-REFB)). Gain error is the deviation of the actual difference between first and last code transitions and the ideal difference between the first and last code transitions. Aperture Delay The aperture delay is the time delay that occurs from when a sampling edge is applied to the HT82V38 until the actual sample of the input signal is held. Both CDSCLK1 and CDSCLK2 sample the input signal during the transition from high to low, so the aperture delay is measured from each clocks falling edge to the instant the actual internal sample is taken.
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Internal Register Descriptions Register Name Configuration MUX Red PGA Green PGA Blue PGA Red Offset Green Offset Blue Offset Address A2 0 0 0 0 1 1 1 1 A1 0 0 1 1 0 0 1 1 A0 0 1 0 1 0 1 0 1 D8 0 0 0 0 0 MSB MSB MSB Internal Register Map Configuration Register The Configuration Register controls the HT82V38s operating mode and bias levels. Bits D6 controls reference clamp voltage. Setting this bit low change OFFSET to high-Z, allowing OFFSET to be driven from external power source. Bit D5 will configure the HT82V38 for the 3-Channel (high) mode of operation. Setting Bit D4 high will enable the CDS mode of operation, and setting this bit low will enable the SHA mode of operation. Bit D3 should always be set low. Bit D2 controls the power-down mode. Setting Bit D2 high will place the HT82V38 into a very low power sleep mode. All register contents are retained while the HT82V38 is in the powered-down state. Bit D1 controls full-scale input range. D1=1, full scale input range will be 2V, D1=0 full scale input range will be 1.6V. Bit D0 controls the output mode of the HT82V38. Setting bit D0 high will enable a single byte output mode where only 8 MSBs of the 16-bit ADC will be output. If bit D0 is set low, then the 16-bit ADC output is multiplexed into two bytes. D8 D7 D6 ClampInt Set to 0 Set to 0 1=Internal* 0=External Note: * Power-on default value Configuration Register Settings D5 3 Channels 1=On* 0=Off D4 CDS operation 1=CDS mode* 0=SHA mode D3 3/4 3/4 0* D2 Power-down 1=On 0=Off (Normal)* D1 Full scale input range 1=2V 0=1.6V* D0 1 byte out 1=On 0=Off * D7 0 RGB/ BGR 0 0 0 D6 Clamp Int D5 3 CH D4 CDS on Data Bits D3 0 ClapC[3] D2 Pwr Dn ClapC[2] D1 D0
Full scale 1byte out input range ClapC[1] ClapC[0] LSB LSB LSB LSB LSB LSB
Red Green Blue 0 0 0 MSB MSB MSB
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MUX Register The MUX Register controls the sampling channel order in the HT82V38. Bits D8 should always be set low. Bit D7 is used when operating in 3-Channel Mode. Setting Bit D7 high will sequence the MUX to sample the red channel first, then the green channel, and then the blue channel. When in this mode, the CDSCLK2 rising edge always resets the MUX to sample the red channel first (see Timing Figure). When Bit D7 is set low, the channel order is reversed to blue first, green second, and red third. The CDSCLK2 rising edge pulse will always reset the MUX to sample the blue channel first. Bits D6, D5, and D4 are used when operating in 1-Channel Mode. Bit D6 is set high to sample the red channel. Bit D5 is set high to sample the green channel. Bit D4 is set high to sample the blue channel. The MUX will remain stationary during 1-Channel Mode. Bit D3 to Bit D0 control 4 bits DAC clamp voltage from 0.45V to 2.7V. D8 D7 3-Channel Set to 0 D6 1-Channel D5 1-Channel D4 1-Channel D3 Clap[3] D2 Clap[2] D1 Clap[1] D0 Clap[0]
1=R-G-B* 0=B-G-R
1=RED* 0=Off
1=GREEN 0=Off*
1=BLUE 0=Off *
1111=2.7V* 1110=2.55V : : 0001=0.6V 0000=0.45V
Note: * Power-on default value MUX Register Settings PGA Gain Register There are three PGA registers for individually programming the gain in the red, green, and blue channels. Bits D8, D7, and D6 in each register must be set low, and bits D5 through D0 control the gain range in 64 increments. See Figure for a graph of the PGA Gain versus PGA register code. The coding for the PGA registers is straight binary, with an all zeros word corresponding to the minimum gain setting (1x) and an all ones word corresponding to the maximum gain setting (5.85x). The PGA has a gain range from 1(0dB) to 5.85(15.3dB), adjustable in 64 steps. The Figure shows the PGA gain as a function of the PGA register code. Although the gain curve is approximately linear in dB, the gain in V/V varies in nonlinear proportion with the register code, according to the following the equation: Gain= 76 76 - G
Where G is the decimal value of the gain register contents, and varies from 0 to 63.
1 5 .3 4 12 ) 9 G A IN -d B ( 6 3 0 0 4 8 12 16 20 24 28 32 36 40 44 48 52 56 6063 P G A r e g is te r v a lu e - - D e c im a l 5 .8 5 5 .0 4 .0 3 .0 2 .0 1 .0 G A IN -V /V ( )
PGA Gain Transfer Function
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D8 Set to 0 0 0 D7 Set to 0 0 0 D6 Set to 0 0 0 D5 MSB 0 0 0 0 0 0 : : 1 1 0 0 0 0 D4 D3 D2 D1 D0 LSB 0* 1 1.0 1.013 : : 5.43 5.85 0.0 0.11 : : 14.7 15.34 Gain (V/V) Gain (dB)
0 0
0 0
0 0
1 1
1 1
1 1
1 1
0 1
Note: * Power-on default value PGA Gain Register Settings Offset Register There are three PGA registers for individually programming the offset in the red, green, and blue channels. Bits D8 through D0 control the offset range from -250mV to +250mV in 512 increments. The coding for the offset registers is sign magnitude, with D8 as the sign bit. Table shows the offset range as a function of the Bits D8 through D0. D8 MSB 0 0 0 0 0 0 0 0 0 0 0 0 : : 1 0 0 : : 1 0 0 0 0 D7 D6 D5 D4 D3 D2 D1 D0 LSB 0* 1 0 +0.98 : : +250 0 -0.98 : : -250 Offset (mV)
0 1 1
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 0
1 0 1
1
1
1
1
1
1
1
1
Note: * Power-on default value Offset Register Settings
Timing Diagrams
SDATA SC LK tL
S
R /W b
tD
H
A2
A1
A0
tD
S
D8
D7
D6
D5
D4
D3
D2
D1
D0
tL
H
SLO AD
Serial Write Operation Timing
SDATA SC LK
R /W b
A2
A1
A0
D8
tR
D7
DV
D6
D5
D4
D3
D2
D1
D0
tL
S
tL
H
SLO AD
Serial Read Operation Timing
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HT82V38
A n a lo g In p u t (R , G , B ) tC
1
tA
D
P ix e l ( N + 2 )
P ix e l ( N + 3 )
P ix e l ( N + 4 )
tA
D
tP
RA
CDSCLK1 tC CDSCLK2 tA
D CLK 1C2
tC
2
tC
2ADF
tA tC tA
DC1
2ADR DC2
tA
D CLK
AD CCLK tO
D
O u tp u t D a ta D7~D0
G
(N -2 )
G
(N -2 )
B (N -2 )
B (N -2 )
R (N -1 )
R (N -1 )
G
(N -1 ) G
(N -1 )
B (N -1 )
B (N -1 )
R (N )
R (N )
G
(N )
G
(N )
B (N )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
3-Channel CCD Mode Timing (select R-G-B mode)
A n a lo g In p u t (G , B ) tC
1
P ix e l ( N + 4 )
P ix e l ( N + 5 )
P ix e l ( N + 6 )
P ix e l ( N + 7 )
tA
D
tA
D
tP
RB
CDSCLK1 tC CDSCLK2 tC tA AD CCLK tO
D 2ADR DC2 1C2
tC
2
tC
2ADF
tA
DC1
tA
D CLK
tA
D CLK
O u tp u t D a ta D7~D0
B (N -2 )
B (N -2 ) G
(N -1 ) G
(N -1 )
B (N -1 )
B (N -1 ) G
(N )
G
(N )
B (N )
B (N ) G
(N + 1 ) G
(N + 1 ) B (N + 1 ) B (N + 1 ) G
(N + 2 )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
2-Channel CCD Mode Timing (select G-B mode)
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P ix e l (N + 8 ) A n a lo g In p u t
tA
D
P ix e l (N + 9 )
P ix e l (N + 1 0 )
P ix e l (N + 1 1 )
tA
D 1
tC CDSCLK1 tC CDSCLK2
tP
RC
1C2
tC
2
tA
DC1
tC AD CCLK
2ADF
tA
D CLK
tA
D CLK
tO
D
O u tp u t D a ta D7~D0
P ix e l (N -2 ) H IG H BYTE
P ix e l (N -2 ) LO W BYTE
P ix e l (N -1 ) H IG H BYTE
P ix e l (N -1 ) LO W BYTE
P ix e l (N ) H IG H BYTE
P ix e l (N ) LO W BYTE
P ix e l (N + 1 ) H IG H BYTE
P ix e l (N + 1 ) LO W BYTE
P ix e l (N + 2 ) H IG H BYTE
1-Channel CCD Mode Timing
P IX E L (N + 2 )
P IX E L (N + 3 )
P IX E L (N + 4 )
A n a lo g In p u t (R , G , B )
tA
D
tC
2
tC CDSCLK2 tA
tC
D CLK
2AD R
2ADF
tP
RA
tA
DC2
tA
D CLK
AD CCLK tO
D
O u tp u t D a ta D7~D0
G
(N -2 )
G
(N -2 )
B (N -2 ) B (N -2 )
R (N -1 )
R (N -1 )
G
(N -1 ) G
(N -1 )
B (N -1 )
B (N -1 )
R (N )
R (N )
G
(N )
G
(N )
B (N )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
3-Channel SHA Mode Timing (select R-G-B mode)
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A n a lo g In p u t (G , B )
P IX E L (N + 4 )
P IX E L (N + 5 )
P IX E L (N + 6 )
P IX E L (N + 7 )
tC
2
tA
D
tC CDSCLK2 tA
D CLK
2ADF
tP
RB
tA
tC
DC2
2AD R
tA
D CLK
AD CCLK tO
D
O u tp u t D a ta D7~D0
B (N -2 )
B (N -2 )
G
(N -1 ) G
(N -1 )
B (N -1 )
B (N -1 )
G
(N )
G
(N )
B (N )
B (N )
G
(N + 1 ) G
(N + 1 ) B (N + 1 ) B (N + 1 ) G
(N + 2 )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
2-Channel SHA Mode Timing (select G-B mode)
P IX E L (N + 8 )
P IX E L (N + 9 )
P IX E L (N + 1 0 ) P IX E L (N + 1 1 ) P IX E L (N + 1 2 )
A n a lo g In p u t
tC CDSCLK2 tA AD CCLK
2ADF
tA
D
tC
2
tP
RC
DC2
tA
D CLK
tA tO
D
D CLK
O u tp u t D a ta D7~D0
P ix e l (N -2 )
P ix e l (N -2 )
P ix e l (N -1 )
P ix e l (N -1 )
P ix e l (N )
P ix e l (N )
P ix e l (N + 1 )
P ix e l (N + 1 )
P ix e l (N + 2 )
P ix e l (N + 2 )
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
H ig h B y te
Low B y te
1-Channel SHA Mode Timing
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HT82V38
Application Circuits
Circuit and Layout Recommendations The recommended circuit configuration for 3-Channel CDS mode operation is shown in Figure. The recommended input coupling capacitor value is 0.1mF (see Circuit Operation section for more details). A single ground plane is recommended for the HT82V38. A separate power supply may be used for DRVDD, the digital driver supply, but this supply pin should still be decoupled to the same ground plane as the rest of the HT82V38. The loading of the digital outputs should be minimized, either by using short traces to the digital ASIC, or by using external digital buffers. To minimize the effect of digital transients during major output code transitions, the falling edge of CDSCLK2 should occur coincident with or before the transient edge of ADCCLK. All 0.1mF decoupling capacitors should be located as close as possible to the HT82V38 pins. When operating in single channel mode, the unused analog inputs should be grounded.
C lo c k In p u ts 1 2 3 3 .3 V 4 5 6 7 8 9 10 11 12 13 D a ta In p u ts 14 3 .3 V CDSCLK1 CDSCLK2 AD CCLK OE DVDD DVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B ) AVDD AVSS V IN R OFFSET V IN G CML V IN B REFT REFB AVSS AVDD SLO AD SC LK SDATA 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0 .1 m F 1 0 m F 0 .1 m F 3 .3 V S e r ia l In p u ts 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F R e d In p u t G re e n In p u t B lu e In p u t 1 .0 m F
H T 8 2 V 3 8 (C D S M o d e )
CDS Application Circuit
Figure shows the recommended circuit configuration for 3-Channel SHA mode. All of the above considerations also apply for this configuration, except that the analog input signals are directly connected to the HT82V38 without the use of coupling capacitors. The analog input signals must already be dc-biased (relative to OFFSET pin) between 0V and 1.60V/2.0V.
C lo c k In p u ts 1 2 3 3 .3 V 4 5 6 7 8 9 10 11 12 13 D a ta In p u ts 14 3 .3 V CDSCLK1 CDSCLK2 AD CCLK OE DVDD DVSS D 7 (M S B ) D6 D5 D4 D3 D2 D1 D 0 (L S B ) AVDD AVSS V IN R OFFSET V IN G CML V IN B REFT REFB AVSS AVDD SLO AD SC LK SDATA 28 27 26 25 24 23 22 21 20 19 18 17 16 15 0 .1 m F 1 0 m F 0 .1 m F 3 .3 V S e r ia l In p u ts 0 .1 m F 0 .1 m F 0 .1 m F 0 .1 m F R e d In p u t G re e n In p u t B lu e In p u t DC Level
H T 8 2 V 3 8 (S H A M o d e )
SHA Application Circuit
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Package Information
28-pin SSOP (209mil) Outline Dimensions
28 A
15 B
1 C C'
14
G H a F
D E
* MO-150
Symbol A B C C D E F G H a
Dimensions in mm Min. 7.40 5.00 0.22 9.90 3/4 3/4 0.05 0.55 0.09 0 0.65 3/4 3/4 3/4 3/4 Nom. 3/4 3/4 3/4 3/4 Max. 8.20 5.60 0.33 10.50 2.00 3/4 3/4 0.95 0.21 8
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Product Tape and Reel Specifications
Reel Dimensions
T2 D
A
B
C
T1
SSOP 28S (209mil) Symbol A B C D T1 T2 Description Reel Outer Diameter Reel Inner Diameter Spindle Hole Diameter Key Slit Width Space Between Flange Reel Thickness Dimensions in mm 330.01.0 100.01.5 13.0
+0.5/-0.2
2.00.5 28.4
+0.3/-0.2
31.1 (max.)
Rev. 1.00
14
July 23, 2009
HT82V38
Carrier Tape Dimensions
D
E F
P0
P1
t
W C
B0
D1
P A0
K0
R e e l H o le IC p a c k a g e p in 1 a n d th e r e e l h o le s a r e lo c a te d o n th e s a m e s id e .
SSOP 28S (209mil) Symbol W P E F D D1 P0 P1 A0 B0 K0 t C Description Carrier Tape Width Cavity Pitch Perforation Position Cavity to Perforation (Width Direction) Perforation Diameter Cavity Hole Diameter Perforation Pitch Cavity to Perforation (Length Direction) Cavity Length Cavity Width Cavity Depth Carrier Tape Thickness Cover Tape Width Dimensions in mm 24.00.3 12.00.1 1.750.10 11.50.1 1.5 1.50
+0.1/-0.0 +0.25/-0.00
4.00.2 2.00.1 8.40.1 10.650.10 2.40.1 0.300.05 21.30.1
Rev. 1.00
15
July 23, 2009
HT82V38
Holtek Semiconductor Inc. (Headquarters) No.3, Creation Rd. II, Science Park, Hsinchu, Taiwan Tel: 886-3-563-1999 Fax: 886-3-563-1189 http://www.holtek.com.tw Holtek Semiconductor Inc. (Taipei Sales Office) 4F-2, No. 3-2, YuanQu St., Nankang Software Park, Taipei 115, Taiwan Tel: 886-2-2655-7070 Fax: 886-2-2655-7373 Fax: 886-2-2655-7383 (International sales hotline) Holtek Semiconductor Inc. (Shenzhen Sales Office) 5F, Unit A, Productivity Building, No.5 Gaoxin M 2nd Road, Nanshan District, Shenzhen, China 518057 Tel: 86-755-8616-9908, 86-755-8616-9308 Fax: 86-755-8616-9722 Holtek Semiconductor (USA), Inc. (North America Sales Office) 46729 Fremont Blvd., Fremont, CA 94538 Tel: 1-510-252-9880 Fax: 1-510-252-9885 http://www.holtek.com
Copyright O 2009 by HOLTEK SEMICONDUCTOR INC. The information appearing in this Data Sheet is believed to be accurate at the time of publication. However, Holtek assumes no responsibility arising from the use of the specifications described. The applications mentioned herein are used solely for the purpose of illustration and Holtek makes no warranty or representation that such applications will be suitable without further modification, nor recommends the use of its products for application that may present a risk to human life due to malfunction or otherwise. Holteks products are not authorized for use as critical components in life support devices or systems. Holtek reserves the right to alter its products without prior notification. For the most up-to-date information, please visit our web site at http://www.holtek.com.tw.
Rev. 1.00
16
July 23, 2009

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